COMMENT ⊗   VALID 00005 PAGES
C REC  PAGE   DESCRIPTION
C00001 00001
C00002 00002	C REC  PAGE   DESCRIPTION
C00003 00003		HARDWARE.
C00006 00004		SOFTWARE.
C00008 00005		COMPARISON OF THE JOINT PROCESSORS.
C00011 ENDMK
C⊗;
C REC  PAGE   DESCRIPTION
C00001 00001
C00002 00002		HARDWARE.
C00005 00003		SOFTWARE.
C00007 00004		COMPARISON OF THE JOINT PROCESSORS.
C00010 ENDMK
C⊗;
	HARDWARE.

Dual port ram interface.

	The dual port ram is implemented as a dual port data bus.
On each joint processor's data bus there is an 8 bit transiver
connected to an 8 bit host - joint I/O bus that is controled by the
host interface. When reading or writing data from a joint's memory,
the host interface first addresses the joint. Then when the host reads
or writes data to/from the interface, the interface waits for the joint
processor's bus to be not locked and a joint instruction fetch signal.
A joint's data bus is locked when the joint reads or writes an area of
memory (shared memory), at an even address. The bus is unlocked when
a read or write is preformed on an odd address. Waiting for a joint
instruction fetch insures that the joint processor will not access
the location being read or writen by the host before the host is
finished.

Each joint processor's data memory consists of:

	Read write memory. 1024 by 8 bits of moderatly fast (200 n.s.)
mos memory.

	Address and control multiplexers. Twelve 2 line to 1 line data
selectors.

	Data bus transiver.

	Bus lockout logic. Which is simply the least significant
address bit of the joint processor clocked by an access to shared ram
by the joint processor.

	Host - joint clock synchronizer. Which, during the joint phase,
streches the ram CS signal until the falling edge of the joint's phase
two clock.


Processor and I/O.

	The encoder interface is a three state 2 to 1 multiplexer.
The processor, output port, DAC, and EPROM program memory are standard
except that the address decoding is only enabled during the phase two
portion of the clock.

Host - joint interface.

	The host - joint interface is the same as the earlier design
except that the joint memory read/write logic has been added and the
ADC and attention request logic have been removed.
	SOFTWARE.

	The basic servo routine remains the same as the earlier
design. Parts of the program that are changed, new, or deleted are:

	The locations of data in ram are changed for the shared ram.

	All of the old position encoder routines have been replaced by
the GETPOS routine which reads the parallel encoder and converts it
from grey to binary.

	The PUTDAC routine has been changed from 12 bits to 8.

	All immediate commands have been deleted.

	The deferred command dispatcher has been changed and a
host - joint deferred command interface routine has been added to
the idle loop.

	The VETBL has been added to correct the dac output.

	The freeze routine has been moved into the reset routine
and is no longer a subroutine.

	All of the 6532 timer and I/O routines have been deleted.

	NMI is no longer being used.

	All accesses to shared ram are "unlocked" within 4 micro
seconds after being locked and all 16 bit accesses to shared ram
are done with the interrupt disabled.
	COMPARISON OF THE JOINT PROCESSORS.

	The new joint prcessor improves on the earlier design in the
following ways:

	By allowing the host direct access to each joint processor's
memory, all host - joint communication is much simpler and faster.
Using shared ram allows reduced host wait time (at least 40%)
when setting new servo position or other syncronized functions,
and greatly reduced joint processor parameter passing overhead
(about 80% less).

	Twice the basic processor cycle than the earlier standard
board.

	Reduced parts count. By using an off board interval generator,
simpler logic on each processor, etc.

	Micro bus compatible 8 bit DAC. What is lost in resolution
(8 bits vs. 12 bits), is regained in speed, less parts, ease of use,
etc.

	Simpler software. By using shared ram, absolute optical
encoders, synchronous intervals, etc. much of the software is
reduced or eliminated.

	Software compatible. By using the same processor and limited
modification of the basic design (I/O and interface paths, etc.),
the joint and host software is able to remain somewhat compatible
with the earlier system.

	Although converting the encoder position from grey to binary
requires an extra 50 micro seconds, the reduced overhead of the
parallel encoder makes up for the delay.